Module Hdl_output

module Hdl_output: sig .. end

Common functions for HDL generators.

This backend is by no means generic, only generic enough to avoid replicated code in VHDL and Verilog generators.

You don't need to know how to use these functions, simply use the VHDL and Verilog frontends!

Setting up and closing the HDL generator

val init_hdl_generator : Circuit.circuit -> string -> string -> string -> (string -> string) -> string

init_hdl_generator circuit hdl_name hdl_ext comment rename

Example: let top_name = init_hdl_generator circuit "Verilog" ".v" "//" (fun x->x) in

Must be called first. Initializes the HDL generator and opens the output file. The string comment is used to make comments. The function rename does optional renaming of port and signal names. It's used in VHDL for creation of extended identiers.

Returns the name of the circuit (top_name) as it was specified with start_circuit top_name.

val close_hdl_generator : unit -> unit

Closes the HDL generator (especially the written file). Must be called last.

Writing the HDL model

val write : string -> unit

Writes an arbitrary string s to the output file. Used to write parts of the HDL output which are not similar enough in VHDL and Verilog to warrant a function of their own.

val write_port_list : unit -> unit

write_port_list ().

Writes a port list. Only used in Verilog, VHDL doesn't have a port list (only a port declaration).

val write_ports : (string -> int -> string) ->
       (string -> int -> string) -> (bool -> string) -> unit

write_ports decl_input decl_output delimiter.

Writes the port declaration. Takes three functions: one to declare an input, one to declare an output and one to close each declaration.

val write_decls : (string -> int -> string) -> (string -> int -> string) -> unit

write_decls decl_reg decl_other.

Writes signal declarations. Takes two functions, one to declare a register and one to declare other signals. Unlike Verilog, VHDL doesn't make a difference between these two types of declarations.

val get_string_of_signal : (string -> string -> string -> int -> string) ->
       (string -> string) ->
       (int -> int -> string -> string) ->
       (string -> string -> string) ->
       (string -> string -> string -> int -> string) ->
       (string -> string -> string -> string) ->
       bool -> Circuit.Signal_map.key -> string

get_string_of_signal signal reg const select un_op bin_op mux.

Auxiliary function used to create the parameter string_of_signal of write_circuit. See VHDL or Verilog generator for its usage which is quite obvious in spite of the appearance.

val write_circuit : string ->
       (bool -> Circuit.signal -> string) ->
       (string -> string -> string -> string) -> unit

write_circuit indent string_of_signal assign.

Writes the actual netlist. The string indent defines the initial indentation of the created text block. The callback function string_of_circuit defines the largest part of the respective HDL syntax, assign defines the syntax of signal assignments.