module Release:Release information.
val version :
* Atomic * removed module stub (KF) * Auxiliary (NEW) * Contains various functions for internal use. (KF) * Circuit * commented out unused modules Circuit_set, Circuit_map and Sink_set (KF) * completed function "string_of_signal" (KF) * Design * mux: fill item list up to length of next power of 2 with last element (KF) * improved error reporting and checking (KF) o strict error checking o configurable strictness of checks for a subset of functions/operators o possibility to locate errors in the source code o debugging support (find_name, find_node) o renaming of illegal/duplicate identifiers during design entry o additional warnings concerning possibly unwanted combinations of arguments to functions/operators o detection of combinational loops during assignment of dangling signals with the <== operator. o checking for unconnected dangling signals (get_circuit) o listing unused inputs (get_circuit) o listing unused circuit nodes in general (get_circuit) o checking for balanced use of start_circuit/get_circuit and circuit/endcircuit o design entry functions and operators (including get_circuit) must not be called before start_circuit * Example * moved from "src" to "additional-src" (KF) * Hdl_output (NEW) * contains common code of VHDL and Verilog generators (KF) * Rename * removed module, all renaming is now done in Design (KF) * Simulate * added multiplications (KF) * fixed several bugs (KF) o select and concat o addition and subtraction o a number of problems concerning masking out the unused bits of the MSW (Signal_eq, Signal_lt, Signal_mux, Signal_reg) o sequence of reg_tasks and sink_tasks ... still not correct * masked unused bits for Sink_ouput for convenience (KF) * added check for potential bug, see Simulate.html (KF) * SystemC * fixed bugs in select, concat and mul (AR) * added ability to query ports by name (AR) (generated C-function "find_simulator_port") * added check for potential bug, see Systemc.html (KF) * removed duplicated struct in *.c file (KF) (#include "*.h" instead) * inputs/outputs/signals are now ordered (KF) * Verify * mark used nodes (with function from Design) (KF) * Verilog * rewritten to use Hdl_ouput as backend (KF) * Vhdl * new module for VHDL output (AR) * rewritten to use Hdl_ouput as backend (KF) (this should guarantee, that the VHDL generator behaves exactly the same as the Verilog generator.) * included functions of hdcaml.vhd in generated file (KF) AR: Andy Ray KF: Karl Flicker
* Verilog * Bug fixed to output ports and properties tied to registers. * Identifies named registers to further reduce _n signals.
* Verilog * Critical bug fixed on output port expressions.
* Circuit ! Removed Signal_nondet. ! Added unique identifier to circuit types. * Added circuit set and map modules. * Added signal and sink set modules. * Design ! Moved all ABV related functions and types to the Verify module. * Simulate * Fixed simulation reset bug. * Fixed select bug. * Verilog * Increased code clarity. Reduced number of _n signal created.
* Design * Added assert_always, assert_always_signal, assume_always, and assume_always_signal. * Simulate * HDCaml circuits can now be simulated within the OCaml language. Simulations produce VCD waveforms recording all internally named signals by hierarchy. See src/example.ml. * Signed and unsigned multiplication is not supported yet. * Systemc * Assuptions now behave as assertions. C support for assertions restricted to: assert_always_signal "name" signal * Bug fix to select primitive (masking above msb). * Waveform ! Changed signal to accept a width instead of an initial value. See src/example.ml. * Signal recording functions can now be called prior to the first cycle.
* Circuit ! Added a unique identifier to each signal and sink. ! Removed signal_id. * Added id_of_signal and id_of_sink. * Design ! Renamed (=>) to (->?): property_a ->? property_b ! Renamed (<=>) to (<->?): property_a <->? property_b * Systemc * Created a new module to generate circuit models in C and SystemC.
* Design ! Renamed (<--) to (<==): signal <== other_signal ! Renamed "label" to (--): "signal_name" -- signal * Waveform * The Waveform module, which generates VCD data, is complete. * An example using the Waveform module is provided in the Example module. * Simulate * Created the Simulate module for simulating circuits within OCaml. Not implemented yet. * Atomic * Created the Atomic module for compiling atomic state transisitons. Not implemented yet.