Module Simulate

module Simulate: sig .. end
Simulate designs within OCaml.

type simulator 
Data structure holding the current state of the simulated circuit.
type port = string * int array 
Input and output data is represented as an array of integers, where each element covers 31 bits. The ordering is little endian: index 0 is the least significant bits. A port, either input or output, provides access to the circuit under simulation. A port provides the associated port name and simulation data array.
val create : Circuit.circuit ->
Pervasives.out_channel ->
simulator * port list * port list
Creates a simulator from a circuit design. Given a circuit and and output channel for VCD, returns the simulator and list of input and output ports for interfacing with the simulator.
val cycle : simulator -> unit
Performs a calculation and advances the simulator one timestep.
val reset : simulator -> unit
Resets the state of the simulator.


There is a situation where the simulator produces wrong results. This occurs when there is combinational logic between registers and outputs (you'll get a INFO when using outputs this way). In this case the results of these outputs are delayed one cycle. You can avoid this problem in one of two ways:

Workaround: The source code is released with the faster but potentially incorrect code activated.

There is a solution which is both fast and correct. It should be implemented in the releases to come.