module Vhdl: sig .. end
VHDL netlist generation.
val output_netlist : Circuit.circuit -> unit
Writes VHDL netlist (<circuit>.vhd) to a file.
Warning
As this code generator is new in HDCaml 0.2.10 it
hasn't been publically tested yet. Please consider
it as experimental!
Workaround for tools which are not VHDL'93 compliant
The VHDL generator creates extended identiers
(names which are delimited with a backslash, e.g. \name\ )
in theses cases:
- subcircuits are used, therefore names
contain double underscores (
"__")
- a name contains capital letters (to allow for case sensitivity)
- a name ends with an underscore
In case your tools aren't VHDL'93 compliant,
simply don't use subcircuits and names with capital letters
or trailing underscores.