Module Vhdl

module Vhdl: sig .. end
VHDL netlist generation.

val output_netlist : Circuit.circuit -> unit
Writes VHDL netlist (<circuit>.vhd) to a file.


As this code generator is new in HDCaml 0.2.10 it hasn't been publically tested yet. Please consider it as experimental!

Workaround for tools which are not VHDL'93 compliant

The VHDL generator creates extended identiers (names which are delimited with a backslash, e.g. \name\ ) in theses cases:

In case your tools aren't VHDL'93 compliant, simply don't use subcircuits and names with capital letters or trailing underscores.