Index of values


(!?) [Verify]
Property NOT.
($) [Verify]
Sequence concatenation.
(&$) [Verify]
Sequence AND (non-length matching).
(&&$) [Verify]
Sequence AND (length matching).
(&&?) [Verify]
Property AND.
(&:) [Design]
Bitwise AND.
(*+) [Design]
Signed multiplication.
(*:) [Design]
Unsigned multiplication.
(++) [Design]
Concatenates two signals together.
(+:) [Design]
Addition.
(-$) [Verify]
Sequence infusion.
(--) [Design]
Applies a label (name) to a signal.
(-:) [Design]
Subtraction.
(->?) [Verify]
Property implication.
(/=:) [Design]
Not equal.
(<+) [Design]
Signed less than.
(<->?) [Verify]
Property equivalence.
(<:) [Design]
Unsigned less than.
(<<+) [Design]
New in 0.2.10.
(<<:) [Design]
Unsigned shift left.
(<=+) [Design]
Signed less than or equal.
(<=:) [Design]
Unsigned less than or equal.
(<==) [Design]
Assigns a value to a dangling signal.
(==:) [Design]
Equal.
(>+) [Design]
Signed greater than.
(>:) [Design]
Unsigned greater than.
(>=+) [Design]
Signed greater than or equal.
(>=:) [Design]
Unsigned greater than or equal.
(>>+) [Design]
Signed shift right.
(>>:) [Design]
Unsigned shift right.
(^:) [Design]
Bitwise XOR.
(|$) [Verify]
Sequence alternation.
(|->) [Verify]
Suffix implication, overlapping.
(|:) [Design]
Bitwise OR.
(|=>) [Verify]
Suffix implication, non-overlapping.
(||?) [Verify]
Property OR.
(~:) [Design]
Bitwise NOT.

A
all_signals [Circuit]
A list of all signals in a circuit.
all_sinks [Circuit]
A list of all sinks in a circuit.
always [Verify]
Property is always true.
any_n [Verify]
Anything for n cycles.
any_n_to_inf [Verify]
Anything for n to inf cycles.
any_n_to_m [Verify]
Anything for n to m cycles.
assert_always [Verify]
Asserts always a property.
assert_always_signal [Verify]
Asserts always a signal.
assertion [Verify]
Asserts a property.
assume [Verify]
Assumes a property.
assume_always [Verify]
Assumes always a property.
assume_always_signal [Verify]
Assumes always a signal.

B
bit [Design]
Selects an individual bit from a signal.
bits [Design]
Splits a signal into a list of bits.

C
check_width [Design]
Checks that a signal has a given width.
check_width_bit [Design]
Checks that a signal is a single bit.
check_width_nonzero [Design]
Checks that a signal has a nonzero width.
check_width_same [Design]
Checks that two signals have the same width.
circuit [Design]
Creates a new subcircuit and namespace.
close_hdl_generator [Hdl_output]
Closes the HDL generator (especially the written file).
concat [Design]
New in 0.2.10.
const [Design]
Creates a constant.
cover [Verify]
Sets a cover point.
create [Simulate]
Creates a simulator from a circuit design.
cycle [Waveform]
Cycles a timestep.
cycle [Simulate]
Performs a calculation and advances the simulator one timestep.

E
empty [Design]
An empty signal.
endcircuit [Design]
Closes a subcircuit.
eventually [Verify]
Eventually.

F
find_name [Design]
Creates an info output when the given name is being used in signal, -- (annotation), input, output, start_circuit or circuit (start of subcircuit).
find_node [Design]
Creates an info output when the given node number is being generated.

G
get_circuit [Design]
Returns the circuit design and resets the internal database.
get_setting_exception_at_error [Design]
Returns current setting of switch above.
get_setting_exception_at_info [Design]
Returns current setting of switch above.
get_setting_strict_checks [Design]
Returns current setting of switch above.
get_string_of_signal [Hdl_output]
get_string_of_signal signal reg const select un_op bin_op mux.
gnd [Design]
A single bit set to 0.

H
high [Design]
New in 0.2.10.

I
id_of_circuit [Circuit]
ID of a circuit.
id_of_signal [Circuit]
ID of a signal.
id_of_sink [Circuit]
ID of a sink.
init_hdl_generator [Hdl_output]
init_hdl_generator circuit hdl_name hdl_ext comment rename
input [Design]
Creates a top-level input.

L
low [Design]
New in 0.2.10.
lsb [Design]
Selects the least significant bit (right most).
lsbs [Design]
Selects all bits except the MSB.

M
msb [Design]
Selects the most significant bit (left most).
msbs [Design]
Selects all bits except the LSB.
mux [Design]
N-Input Mux: mux ctrl items
mux2 [Design]
2-input mux: mux2 select on_high on_low.

N
never [Verify]
Property is never true.

O
one [Design]
Creates a constant 1.
ones [Design]
Creates a constant of 111's.
open_vcd [Waveform]
Creates a new VCD waveform database.
order_signals_description [Circuit]
Topologically ordered based on description.
order_signals_sequential [Circuit]
Topologically orders all signals.
output [Design]
Assigns a top-level output.
output_model [Systemc]
Writes a C model (<circuit>.h, <circuit>.c ) and a SystemC wrapper (<circuit>_sc.h).
output_netlist [Vhdl]
Writes VHDL netlist (<circuit>.vhd) to a file.
output_netlist [Verilog]
Writes Verilog netlist (<circuit>.v) to a file.

P
plus [Verify]
Anything 1 or more.
prop [Verify]
Creates a property from a single bit signal.
propseq [Verify]
Creates a property from a sequence.
propseq_w [Verify]
Creates a property from a weak sequence.
psl_of_property [Circuit]
PSL code of a property.
psl_of_sequence [Circuit]
PSL code of a sequence.

R
raise_exception_at_error [Design]
Allows to inhibit the raising of an exception after occurrence of an error, that means the program is further executed.
raise_exception_at_info [Design]
Causes an info to have the same consequences as an error, i.e.
reg [Design]
Register.
repeat [Design]
Repeats concatenation N times.
repeat_n [Verify]
Consecutive repetition.
repeat_n_to_inf [Verify]
Consecutive repetition.
repeat_n_to_m [Verify]
Consecutive repetition.
repeat_plus [Verify]
Sequence repetion (1 or more).
repeat_star [Verify]
Sequence repetion (0 or more).
reset [Simulate]
Resets the state of the simulator.
rigid [Verify]
Creates a non-deterministic, rigid signal for verification.

S
scope [Waveform]
Creates a new sub-scope.
select [Design]
Selects a section of a signal.
seq [Verify]
Creates a sequence from a single bit signal.
set_strict_checks [Design]
Switch to turn the strict checks on and off for functions/operators of class 2 (see definition above).
signal [Waveform]
Creates a new signal and provides a function to record signal values.
signal [Design]
signal name w.
split [Design]
Splits a signal into two equal parts.
star [Verify]
Anything (0 or more).
start_circuit [Design]
Starts a new circuit design.
string_of_signal [Circuit]
String of a signal.

U
until [Verify]
Strong until.
until_w [Verify]
Weak until.

V
vdd [Design]
A single bit set to 1.
version [Release]
HDCaml version.

W
width [Design]
Width of a signal.
width [Circuit]
Width of a signal.
within [Verify]
(PSL s1 within s2)
write [Hdl_output]
Writes an arbitrary string s to the output file.
write_circuit [Hdl_output]
write_circuit indent string_of_signal assign.
write_decls [Hdl_output]
write_decls decl_reg decl_other.
write_port_list [Hdl_output]
write_port_list ().
write_ports [Hdl_output]
write_ports decl_input decl_output delimiter.

Z
zero [Design]
Creates a constant 0.