HDCaml is a hardware description
language (HDL) embedded in Objective Caml (OCaml).
See its website for
This web page describes a set of changes that I made
in the course of my diploma thesis to improve some
features of HDCaml.
See previous updates
for versions 0.2.9.1 and 0.2.9.2.
for links to related projects and for the slides (in german)
of my presentations of the diploma thesis.
This version contains many improvements over 0.2.9
(see Release.html for a
complete list of changes).
The main topics are:
(Licence: GNU LGPL)
- better detection of errors and design rule violations
- more informative error messages including line numbers
- new and very useful debug features (find_name, find_node)
- corrected and completed built-in simulator
- new VHDL generator (written by Andy Ray)
- merged common code of generators for Verilog and VHDL
- bugfixes for SystemC code generator (written by Andy Ray)
Documentation: HDCaml 0.2.10 language reference manual